Predictive Modeling of Wafer Acceptance Test Parameters for Semiconductor Yield Enhancement

Abstract

Wafer acceptance testing provides important electrical information for evaluating semiconductor quality before assembly and packaging. This study presents a predictive modeling framework that uses wafer acceptance test parameters to support yield enhancement. Historical wafer records were prepared using threshold voltage, leakage current, drive current, resistance, capacitance, breakdown voltage, spatial variation, tool identity, and process route. Multiple linear regression, random forest, and gradient boosting models were developed and compared. The results showed that gradient boosting achieved the highest prediction accuracy, followed by random forest and linear regression. Threshold-voltage variation, leakage current, contact resistance, breakdown voltage, and centre-to-edge differences were identified as the strongest yield indicators. The proposed approach can help engineers detect wafers at risk of yield loss, identify important electrical causes, and improve screening decisions. It can also support faster process correction and more stable semiconductor manufacturing performance during production.